A Cost-effective Technique to Mitigate Soft Errors in Logic Circuits

The soft error rates (SER) in logic circuits increase quickly as devices scale. Existing techniques to mitigate soft errors in logic circuits often incur large overheads. In this work, we propose a ’lightweight’ technique that detects soft errors in logic circuits, utilizing the concept of temporal sampling. The technique adds some modifications to the conventional pipeline to allow data to be sampled twice in time and compared for integrity. The area, power, and timing overheads of modifying a 32-bit multiplier to support the technique are respectively 19.3%, 7.6%, and 6.4%. Comparing to existing soft error detection circuit techniques, our technique incurs lower overheads. The technique is also applicable in scaled process technologies.